Reproducible Benchmarking for Capacitated Multi-Agent Pickup and Delivery
Current research · RAIL Lab · Georgia Tech
I am building a reproducible framework for capacitated many-to-many multi-agent pickup and delivery (MAPD) in payload-constrained logistics environments, with identical task traces, maps, starting states, horizons, and seeds for fair comparison.
Benchmarking is the first phase, not the endpoint: a frozen runnable baseline, explicit Task, Agent, ScheduleEvent, and WorldState models, replayable event logs, and invariant checks for capacity, ordering, assignment, conflicts, deadlines, and executed cost.
After validation, I will develop and evaluate a many-to-many MAPD algorithm. Initial work uses TPMC and RMCA under capacity 1, with A* estimates and reservation-table space-time A*; later experiments will study higher-capacity insertion, allocation, routing, throughput, planning time, and execution cost.
Research methods
- Frozen runnable repository baseline
- Replayable task traces and identical seeds
- Invariant-driven validation
- A* shortest-path estimates
- Reservation-table space-time A*
- TPMC and RMCA initial baselines
- Independent event-log replay
- Multi-seed evaluation
- Algorithm development after benchmark validation
FPGA Implementation of Residue Number System based Digital Differentiator
Prior Research · Advised by Prof. Tarun Kumar Rawat · Netaji Subhas Institute of Technology
- The Problem: Traditional binary arithmetic introduces severe
computational carry-propagation delays and power overheads when executing high-frequency
digital signal processing on resource-constrained or edge devices.
- The Approach: Evaluated alternative mathematical frameworks by
designing and implementing a full-band Digital Differentiator using a three-moduli
Residue Number System (RNS). Built the underlying hardware description architectures in
Verilog HDL and simulated execution workflows on an Artix-7 FPGA target using the Xilinx
Vivado design suite.
- The Outcome: Demonstrated that custom-tailored RNS modular structures
compress arithmetic bottlenecks and decrease total processing time for edge digital
systems compared to standard infinite impulse response configurations.
Conference Presentation: “FPGA Implementation of Residue Number
System based Digital Differentiator” — peer-reviewed and presented at The
International Conference on Signal Processing, VLSI and Communication Engineering
(ICSPVCE), Delhi Technological University.